In a semiconductor integrated circuit which uses a high precision clock signal, a PLL is widely used as a circuit that generates the high precision clock signal. This PLL uses a voltage controlled oscillator whose oscillation frequency or phase is controlled such as to generate the high precision clock signal. In a routine practice for constructing the voltage controlled oscillator, a plurality of delay circuits, whose delay time may be controlled by a voltage, are interconnected in a ring. The delay circuits are interconnected in the ring so that the last stage output signal will be phase-inverted with respect to the input signal of the initial stage so as to be fed back in this phase-inverted state to the initial stage input signal, thereby causing the oscillations. The oscillation frequency may be controlled by a voltage applied to a control terminal.
It is well-known that the delay circuit or the voltage controlled oscillator suffers from variations in the oscillation frequency or in the delay time by power supply noises. Among conventional measures taken to cope with this problem, there is such a measure disclosed in Patent Document 1. Specifically, Patent Document 1 shows a clock generation circuit provided with a delay circuit and a voltage controlled oscillator of the above type and which is able to generate a clock signal of small jitter against power supply voltage variations caused e.g., by power supply noises. FIG. 8 depicts a circuit diagram showing a conventional delay circuit and a conventional voltage controlled oscillator used in the PLL circuit disclosed in Patent Document 1. Referring to FIG. 8, a ring oscillator type oscillation circuit 41 includes three sets each made up of pair CMOS inverters and three voltage controlling MOS transistors Q11, Q12 and Q13 associated with the three sets. Each MOS transistor is provided common to the associated pair CMOS inverters. The CMOS inverters of each pair are constructed in the form of a differential circuit to execute a complementary operation. The pair inverter sets are arranged to form a ring oscillator. A differential amplifier is connected at the trailing stage to act as a buffer gate 42 to output differential signals as a single-ended signal. Since the ring oscillator type oscillation circuit 41 operates differentially, the operation margin may be improved. In addition, the gate voltages of the MOSFETs, connected in cascode, are lowered by voltage division to reduce the signal voltage of each CMOS inverter to raise the oscillation frequency.
Moreover, in this ring oscillator type oscillation circuit 41, a plurality of the MOSFETs, connected in cascode to the PMOS sides of the three sets of the CMOS inverters, is replaced by a single common MOSFET Q21, thereby decreasing variations of the signal amplitudes of the respective CMOS inverters.
Referring to FIG. 8, an N-channel MOS transistor Q10 forms a current mirror circuit with N-channel MOS transistors Q11 to Q13. That is, the currents proportionate to a current Iv flowing through the N-channel MOS transistor Q10 are controlled to flow through Q11, Q12 and Q13. The current Iv is a control current converted from a control voltage by a voltage-to-current converter, not shown, and controls the oscillation frequency of the oscillation circuit. The PMOS transistor Q21 is used for limiting the output amplitude of each inverter circuit. A constant bias voltage Vb is applied by a smoothing circuit 43 to the gate of the PMOS transistor Q21. This bias voltage determines the output voltages of the inverter circuits. In Patent Document 1, the smoothing circuit 43 has a longer CR time constant, so that, even if the power supply voltage VDD is changed with e.g., power supply noises, it is possible to prevent variations in the bias voltage to prevent variations in the output voltage of each inverter circuit and hence the variations in the delay time of each inverter circuit. In FIG. 8, each pair inverter circuit represents a delay circuit that delays the differential signals. Thus, FIG. 8 in its entirety represents the voltage controlled oscillator 41. In FIG. 8, the voltage-to-current converter, among the component elements of the voltage controlled oscillator, is not shown. It should be noted that a voltage-to-current converter, configured to prevent variations of the current Iv ascribable to power supply noises, is shown and described in Patent Document 1.